Manufacturing of integrated circuits is becoming increasingly complex as the device density of such circuits increases. High density circuits require closely spaced interconnect lines and multiple layers of materials and structures, all in micron and submicron dimensions. Surface planarity of the semiconductor deteriorates significantly once a metal is covered with an oxide layer. The surface of the layer will have a topography which in general will conform to the sublayer. The prior structures and layers create surface topography with areas of irregular elevation, troughs and the like. As the layers increase, the irregularities become more pronounced. Such topography adversely effects the fine pattern resolution and depth-of-focus limitations required for lithography, deposition of films, etching of small dimension interconnect lines and the overall yield and performance of the integrated circuit. Consequently it is desirable to planarize the layers to minimize irregularities in the topography of the surface and thus enhance the processing and performance of the integrated circuit.
Planarization is a process used to create smooth, planar layers on wafers. Chemical Mechanical Polishing (CMP) is one technique of planarization which essentially provides for polishing a wafer by rubbing a polishing pad against the wafer to grind the surface layer. Often, the polishing pad is saturated with an abrasive slurry solution which may aid the planarization. A common slurry used is colloidal silica in an aqueous KOH solution. CMP tools are well known in the art, such tools are disclosed in U.S. Pat. Nos. 3,841,031 and 4,193,226. The tools include a polishing wheel with the wafer attached. As the wheel rotates the wafer is forced against a wetted polishing surface and the surface is planarized.
A critical aspect of the planarization process is determining when to cease planarizing or polishing. Predicting such end-point is very difficult. Various methods of determining the end point are known in the art.
One method is by visual inspection. According to this method, the wafers are periodically taken from the CMP machine and inspected. Generally, a metal is chosen with a color distinct from the overlying layer to be removed, such that the color change becomes visible as the overlying layer is polished. The CMP is then stopped.
U.S. Pat. No. 5,265,378 discloses another method of end-point detection during the CMP process. A contact structure, similar to the functional device features to be fabricated, is formed atop a wafer and extends to a height where termination of polishing is desired. The contact structure is not a layer but is like a device structure such as a metallic button or inoperative gate. The contact structure is formed by appropriate fabrication steps such as deposition, etching and mastring. It is preferred that such contact structures be formed in "sacrificial" areas of the wafer where active components will not be affected. In another embodiment of the '378 patent, vias are fabricated by ion milling or etching or the like, and then filled with conductive material, thus providing a conductive path which is coupled to a measuring apparatus. A change in resistance/impedance is observed when the contact structure becomes exposed to a slurry during polishing. The CMP process is then terminated. In contrast to this prior art technique, the method of the present invention forms a functional layer of a desired thickness and then a simple layer of trace dimension is formed atop the functional layer. The trace layer will serve to trigger termination of the planarization process when it is reached. The trace layer does not require elaborate fabrication steps and it does not impact or adversely affect the electrical properties of the functional layer or the circuit features. Thus, there is no limitation on placement of the trace layer as there is with the contact structure disclosed in the prior art patent.
U.S. Pat. No. 5,272,117 also discloses a method of planarizing a layer and endpoint detection during a CMP or etch-back process. A first layer is formed over an integrated circuit layer. Another thick layer is formed over the first layer and the thick layer is etched to expose portions of the first layer and to form spacers of a desired thickness adjacent to the sidewall formations of the first layer. A second layer is formed over the first layer and the spacers, then polishing or an etch-back operation is performed until the spacers are detected by either chemical or electrical means. Another embodiment of the invention provides for different rates of planarization between the spacers and the second layer of material whereby the second layer of material planarizes at a faster rate than the spacer material. The endpoint is signaled by a change in polishing pressure. Another detection mechanism is by detecting a chemical change in the slurry. Like the '378 patent discussed above, this prior art technique utilizes a structure which in this case is a sidewall formation and spacer, not a layer, to terminate the planarization process. Again, elaborate fabrication steps are necessary to practice the method of the '117 patent.
Another end-point detection technique known in the art utilizes selective etching to prevent further etching of a layer. Such techniques are dependent upon the chemistry of the slurry used and the selectivity ratios of the layers to be etched. An example of this type of method is disclosed in U.S. Pat. No. 5,169,491 whereby a layer of undoped silicon dioxide is formed atop a wafer and then a layer of borophosphosilicate glass (BPSG) is formed on the silicon dioxide layer. The BPSG layer is polished using a slurry with a significant etch rate for the BPSG layer whereby etching of the BPSG layer proceeds at a greater rate relative to etching of the SiO.sub.2. This limits etching of the SiO.sub.2 layer which acts as an endpoint. This patent requires the use of a slurry with specified pH and solids concentration, and requires selection of materials with significant selectivity ratios. The method will not work if the etch selectivity of the two materials is not significantly different.
All of the above prior art methods require elaborate fabrication steps. Many of the methods require metallization steps, etching steps or fabrication of numerous layers of different materials. Such fabrication steps consume time which decrease throughput and increase cost. Further, one important limitation of some of the prior art is that the structures or spacers utilized for detecting the end-point of the process may affect the function of the device and thus their placement and size are a limitation. In addition, other methods allow only certain types of materials to be used whereby polishing rates must be different, or etch selectivity is a factor, all of which limit the materials that can be used. As will become apparent by the description below, the invention disclosed herein overcomes these limitations by providing a simple, easily incorporated process for forming a planarized layer.